Do you have experience with digital IC design on pure digital and mixed signal chips?✱

Do you have experience with the language System Verilog?✱

Do you have experience in simulating your designs or netlists with annotated timing (gate level simulation)?✱

Do you have experience in verifying digital chips?✱

Do you have experience with the verification methodology UVM?✱

Do you have experience quantifying and tracking the verification status of the project: e.g code coverage, functional coverage,...?✱

Do you have experience in writing synthesis constraints that match your designs needs?✱

Do you have experience with designing chips taking DFT into account?✱

What is your level of proficiency in English?✱

Are you willing to move to Belgium if you're currently living in another country?✱