Senior ASIC Designer

Jerusalem, Israel /
R&D – Hardware /
Full time
At Mobileye, we foster a hybrid-friendly environment, combining work from office and home.

Which team will you join?
You will join the ASIC Department which is responsible for the design of the SoC for Automotive Applications "EyeQ".
The ASIC Team is now designing the 7th EyeQ generation - AKA EyeQ Ultra / AV on Chip.

What will you do?

    • You will work on developing the next generation of Mobileye SoC for ADAS and AV.
    • Integrate third parties and proprietary IPs in a multi-clock domain system on chip.
    • Design and implement new proprietary IPs and system features.
    • Verification, synthesis, static timing analysis, and closure.
    • Power and Area Optimizations.
    • You will become familiar with design environment, flow, tools, methodologies and optimization methods

All you need is:

    • BSc in Electrical Engineering
    • 3 years of experience in logic design (Verilog / VHDL) and synthesis.
    • Experience in working with Design-Compiler-Topographical flow.
    • Experience with synthesis, timing constraints and exceptions for multiple clock domains in the SoC.
    • Good Tcl scripting skills - advantage
    • Perl / Python scripting skills - advantage
    • Both Verilog and VHDL knowledge - advantage
    • Place-And-Rout and/or Clock-Tree-Synthesis experience - advantage.
    • Experienced with large SoC complexities and challenges - advantage.
    • Experience with TSMC advanced technology nodes - advantage

Mobileye changes the way we drive, from preventing accidents to semi and fully autonomous vehicles. If you are an excellent, bright, hands-on person with a passion to make a difference come to lead the revolution!