Spring Co-Op, Mixed Signal Modeling & Verification (BO)
Chandler, Arizona
Hardware & Software – Hardware /
Intern/Co-op /
On-site
For nearly four decades, Cirrus Logic has been propelled by the top engineers in mixed-signal processing. Our rockstar team thrives on solving complex challenges with innovative end-user solutions for the world's top consumer brands. Cirrus Logic is also known for its award-winning culture, built on a foundation of inclusion and fairness, meaningful community engagement and delivering enjoyable employee experiences at every turn. But we couldn’t do it without our extraordinary workforce – and that’s where you come in. Join our team and help us continue to make Cirrus Logic an exceptional place to grow your career!
We are seeking a creative and hardworking summer intern to join our outstanding Analog/Mixed-Signal Verification team. You will collaborate with systems and design teams to facilitate top down design methodology. You will also work with chip and DV leads to plan, setup, & execute AMS/UVM verification. This position will play a vital role streamlining development methodology for our organization. We are proud of our outstanding environment and multi-faceted culture. Join us and be part of our journey, innovating incredible technology on a global basis!
RESPONSIBILITIES:
- You will contribute to a team that performs verification planning and AMS simulation on full custom ASICs
- Develop behavioral models using SystemVerilog real number modeling (sv-rnm), user-defined types(sv-udt), & Verilog AMS
- Develop test plans, test benches, and verification methodologies to verify the microarchitecture and design
- Independent Interpretation of analog circuit schematics into abstract models
- Collaborate with system architects and designers to streamline architectural exploration of next-generation IP
- Collaborate with UVM verification engineers to ensure all verification components are used for AMS-UVM flow
- Collaborate with multi-functional teams to streamline chip-level integration
- Performing regression debug support and other flow/infrastructure development
REQUIRED KNOWLEDGE, SKILLS AND EXPERIENCE:
- Currently pursuing a MS or higher in Electrical Engineering or Computer Engineering
- Strong background in System Verilog for real number modeling (RNM) modeling, test bench development & verification
- Solid understanding and hands on experience on the design of mixed signal designs
- Organized and detailed with strong communication skills
- Possess outstanding analytical and problem-solving skills
- Hard-working and ability to operate in dynamic environment
- Strong knowledge of System Verilog RTL debug
PREFERRED KNOWLEDGE, SKILLS AND EXPERIENCE
- Python skills would be highly desirable
- Teaming closely with digital/analog designers, applications engineers, and manufacturing test to support both pre-silicon verification and post silicon validation efforts
- Knowledge of signal processing and System Verilog Assertions and PSL Assertions
- Ability to create, evaluate, debug, and improve a verification process
- UVM experience would be highly desirable
- Prior experience with SDF annotation in AMS simulations
- Prior experience with UPF or CPF
This internship is on-site. This opportunity is available for the spring semester only. It is available only to students currently enrolled in a MS or PhD program in Electrical Engineering maintaining a GPA of 3.6 or above, and who will be returning to school for at least one semester following completion of his/her internship. Candidate must be available for full-time employment during the internship.
Diversity drives innovation at Cirrus Logic. Different approaches, ideas and points of view are both valued and respected, and employees are rewarded for their skills, experience and performance. Additionally, Cirrus Logic is an Equal Opportunity/Affirmative Action Employer, and we do not discriminate on the basis of race, color, national origin, pregnancy status, marital status, gender, age, religion, physical or mental disability, medical condition, veteran status, sexual orientation, gender identity, genetic information or any other characteristic protected by law.
